This invention relates to semiconductor devices, more particularly, semiconductor devices having a new conductive interconnection structure, and a method for manufacturing the same.
The packing densities and the degree of integration of integrated circuits are increasing more and more and multilevel interconnections are formed in integrated circuits which tend to increase the number of levels of the device. The reliability of multilevel interconnections is an important problem in semiconductor device productions and a large number of techniques to improve the reliability have been proposed. In general, multilevel interconnections are formed by depositing alternate lines of patterned interconnections separated by dielectric layers. The lines of patterned interconnections are usually, of metal, especially aluminum. The multiple metal-interconnection lines are interconnected by way of through holes provided in the dielectric layers. The interconnections by way of the through holes between multiple metal-interconnection lines are formed by creating holes in the dielectric layer which exists over a first metal-interconnecting line, depositing a second metal layer over the dielectric layer and into the holes, thereby forming a metal interconnection between the first metal line and the second metal layer, and patterning the second metal layer to form a second metal-interconnecting line. In such a process, the steps at the holes of the dielectric layers make the metal lines uneven and the steps at the edges of the patterned metal-interconnections make the dielectric layers uneven. Thus, when laminated layers are increased in number, disconnections and/or short circuits in the interconnections are possible. Further, at the steps of the through holes of a phospho-silicate glass (PSG) layer deposited over a first metal-interconnecting line which is formed over a silcon dioxide layer, the glass flow method for providing a gentle slope to the peripheries of the through holes cannot be used due to the reaction of aluminum with silicon dioxide at temperatures above 500.degree. C. It is, therefore, not recommended to laminate more than 3 to 5 layers of interconnections.